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caution: as with all semiconductor ics, it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by electrostatic discharge (esd). gigabit ethernet transceiver chip with dual serial i/o and differential pecl clock inputs HDMP-1638 transceiver technical data features ? ieee 802.3z gigabit ethernet compatible, supports 1250 mbd gigabit ethernet ? based on x3t11 10-bit specification ? low power consumption ? transmitter and receiver functions incorporated onto a single ic ? 10 mm, 64-pin plastic package ? 5 volt tolerant i/os ? 10-bit wide parallel ttl compatible i/os ? single +3.3 v power supply ? differential pecl clock inputs ? dual serial i/o with receive select ? 2kv esd protection on all pins applications ? 1250 mbd gigabit ethernet interface ? high speed proprietary interface ? backplane serialization/bus extender description the HDMP-1638 transceiver is a single silicon bipolar integrated circuit packaged in a plastic qfp package. it provides a low-cost, low-power physical layer solution for 1250 mbd gigabit ethernet or proprietary link interfaces. it provides complete serialize/ deserialize (serdes) for copper transmission, incorporating both the gigabit ethernet transmit and receive functions into a single device. this chip is used to build a high speed interface (as shown in figure 1) while minimizing board space, power and cost. it is compatible with the ieee 802.3z specification. the transmitter section accepts 10-bit wide parallel ttl data and serializes this data into two high speed serial data streams. the parallel data is expected to be 8b/10b encoded data, or equivalent. this parallel data is latched into the input register of the transmitter section on the rising edge of the 125 mhz reference clock (used as the transmit byte clock). the transmitter sections pll locks to this user supplied 125 mhz byte clock. this clock is then multiplied by 10, to generate the 1250 mhz serial signal clock used to generate the high speed outputs. the high speed outputs are capable of interfacing directly to copper cables for electrical transmission or to a separate fiber optic module for optical transmission. the receiver section allows for the selection of one of two serial electrical data streams at 1250 mbd and recovers the original 10-bit wide parallel data. the receiver pll locks onto the incoming serial signal and recovers the high speed serial clock and data. the serial data is converted back into 10-bit parallel data, recognizing the 8b/10b comma character to establish byte alignment.
2 figure 1. typical application using the HDMP-1638. HDMP-1638 protocol device serial data out receiver section pll transmitter section bytsync enbytsync refclk serial data in pll rxsel the recovered parallel data is presented to the user at ttl compatible outputs. the receiver section also recovers two 62.5 mhz receiver byte clocks which are 180 degrees out of phase with each other. the parallel data is properly aligned with the rising edge of alternating clocks. for test purposes, the transceiver provides for on-chip local loop- back functionality controlled through an external input pin. additionally, the byte synchro- nization feature may be disabled. this may be useful in proprietary applications which use alternative methods to align the parallel data. HDMP-1638 block diagram the HDMP-1638 was designed to transmit and receive 10-bit wide parallel data over high- speed serial lines. the parallel data applied to the transmitter is expected to be encoded per the gigabit ethernet specification, which uses an 8b/10b encoding scheme with special reserve characters for link management purposes. in order to accomplish this task, the HDMP-1638 incorporates the following: ? ttl parallel i/os ? high speed phase locked loops ? parallel to serial converter ? serial clock and data recovery ? comma character recognition ? byte alignment circuitry ? serial to parallel converter figure 2. HDMP-1638 transceiver block diagram. ?douta tx pll/clock generator ?refclk ?dina rxcap0 rxcap1 rbc0 rbc1 bytsync enbytsync output driver internal tx clocks input latch data byte rx[0-9] txcap1 txcap0 data byte tx[0-9] internal rx clocks loopen internal loopback output select frame mux rx pll/clock recovery input select frame demux and byte sync input sampler ?doutb ?dinb rxsel
3 input latch the transmitter accepts 10-bit wide ttl parallel data at inputs tx[0..9]. refclk (from this point forward, refclk is defined as the difference between the user- provided pecl reference clocks, refclk) is used as the transmit byte clock. the tx[0..9] and refclk signals must be properly aligned, as shown in figure 3. tx pll/clock generator the transmitter phase locked loop and clock generator (tx pll/clock generator) block is responsible for generating all internal clocks needed by the transmitter section to perform its functions. these clocks are based on the supplied reference byte clock. refclk is used as both the frequency reference clock for the pll and the transmit byte clock for the incoming data latches. it is expected to be 125 mhz and properly aligned to the incoming parallel data (see figure 3). this clock is then multiplied by 10 to generate the 1250 mhz clock necessary for the high speed serial outputs. frame mux the frame mux accepts the 10-bit wide parallel data from the input latch. using internally generated high speed clocks, this parallel data is multiplexed into the 1250 mbd serial data stream. the data bits are transmitted sequentially, from the least significant bit (tx[0]) to the most significant bit (tx[9]). output select the output select block provides for an optional internal loopback of the high speed serial signal for testing purposes. in normal operation, loopen is set low and the serial data stream is placed at both douta and b. when wrap-mode is activated by setting loopen high, the douta, b pins are held static at logic 1 and the serial output signal is internally wrapped to the input select box of the receiver section. input select the input select block determines whether one of two pairs of signals dina, b or the internal loop-back serial signal is used. in normal operation, loopen is set low and the serial data is accepted at dina or b. rxsel selects if serial data at dina or b will be parallelized. if rxsel is low then dina will be selected. if rxsel is high then dinb will be selected. when loopen is set high, the high speed serial signal is internally looped-back from the transmitter section to the receiver section. this feature allows for loop back testing exclusive of the transmission medium. rx pll/clock recovery the rx pll/clock recovery block is responsible for frequency and phase locking onto the in- coming serial data stream and recovering the bit and byte clocks. an automatic locking feature allows the rx pll to lock onto the input data stream without external pll training controls. it does this by continually frequency locking onto the 125 mhz reference clock, and then phase locking onto the input data stream. an internal signal detection circuit monitors the presence of the input, and invokes the phase detection as the data stream appears. once bit locked, the receiver generates the high speed sampling clock at 1250 mhz for the input sampler, and recovers the two 62.5 mhz receiver byte clocks (rbc1/rbc0). these clocks are 180 degrees out of phase with each other, and are alternately used to clock the 10-bit parallel output data. input sampler the input sampler is responsible for converting the serial input signal into a retimed serial bit stream. in order to accomplish this, it uses the high speed serial clock recovered from the rx pll/clock recovery block. this serial bit stream is sent to the frame demux and byte sync block.
4 symbol parameter units min. typ. max. t setup setup time nsec 1.5 t hold hold time nsec 1.0 t _txlat [1] transmitter latency nsec 3.5 bits 4.4 frame demux and byte sync the frame demux and byte sync block is responsible for restoring the 10-bit parallel data from the high speed serial bit stream. this block is also responsible for recognizing the comma character (or a k28.5 character) of positive disparity (0011111xxx). when recognized, the frame demux and byte sync block works with the rx pll/clock recovery block to properly align the receive byte clocks to the parallel data. when a comma character is detected and realignment of the receiver byte clocks (rbc1/rbc0) is necessary, these clocks are stretched, not slivered, to the next possible correct alignment position. these clocks will be fully aligned by the start of the second 2-byte ordered set. the second comma character received shall be aligned with the rising edge of rbc1. as per the 8b/10b encoding scheme, comma characters must not be transmitted in consecutive bytes to allow the receiver byte clocks to maintain their proper recovered frequencies. output drivers the output drivers present the 10-bit parallel recovered data byte properly aligned to the receive byte clocks (rbc1/rbc0), as shown in figure 5. these output data buffers provide ttl compatible signals. signal detect the signal detect block examines the differential amplitude of the inputs dinb. when this input signal is too small, it outputs a logic 0 at sig_det (refer to sig_det pin definition for detection thresholds). when the signal at dinb is of a valid amplitude, sig_det is set to logic 1. note: 1. the transmitter latency, as shown in figure 4, is defined as the time between the latching in of the parallel data word (as triggered by the rising edge of the transmit byte clock, refclk) and the transmission of the first serial bit of that parallel word at either output pair (defined by the rising edge of the first bit transmitted). HDMP-1638 (transmitter section) timing characteristics t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v
5 figure 3: transmitter section timing. figure 4: transmitter latency. data data tx[0]-tx[9] t setup t hold refclk data data data 0.0 v ac 2.0 v 0.8 v data byte b data byte c tx[0]-tx[9] data byte a ?douta,b 0.0 v ac data byte b t_txlat t6 t7 t8 t9 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t0 t1 t2 t3 t4 t5 refclk
6 figure 5: receiver section timing figure 6: receiver latency symbol parameter units min. typ. max. f_lock frequency lock at powerup m s 500 b_sync [1,2] bit sync time bits 2500 t valid_before time data valid before rising edge of rbc nsec 2.5 t valid_after time data valid after rising edge of rbc nsec 1.5 t duty rbc duty cycle % 40 60 t a-b [4] rising edge time difference between rbc0 and rbc1 nsec 7.5 8.5 t _rxlat [3] receiver latency nsec 22.4 bits 28.0 notes: 1. this is the recovery time for input phase jumps, per the fibre channel specification x3.230-1994 fc-ph standard, sec 5.3. 2. tested using c pll =0.1 m f. 3. the receiver latency, as shown in figure 6, is defined as the time between receiving the first serial bit of a parallel data word (defined as the first edge of the first serial bit) and the clocking out of that parallel word (defined by the rising edge of the receive byte clock, either rbc1 or rbc0). 4. guaranteed at room temperature. HDMP-1638 (receiver section) timing characteristics t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v data data rx[0]-rx[9] t valid_before t valid_after rbc1 k28.5 data data 1.4 v 2.0 v 0.8 v bytsync rbc0 t a-b 2.0 v 0.8 v 1.4 v data byte a data byte d rx[0]-rx[9] data byte d ?dina,b 1.4 v t_rxlat r5 r6 r7 r8 r9 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r2 r3 r4 r5 rbc1/0 data byte c
7 symbol parameter units min. max. v cc supply voltage v -0.5 5.0 v in,ttl ttl input voltage v -0.7 v cc +2.8 v in,hs_in hs_in input voltage v 2.0 v cc i o,ttl ttl output source current ma 13 t stg storage temperature c -65 +150 t j junction temperature c 0 +150 HDMP-1638 (trx) absolute maximum ratings t a = 25 c, except as specified. operation in excess of any one of these conditions may result in permanent damage to this device. parallel clock rate serial baud rate (mhz) (mbaud) min. max. min. max. 124.0 126.0 1240 1260 HDMP-1638 (trx) guaranteed operating rates t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. f nominal frequency (for gigabit ethernet compliance) mhz 125 f tol frequency tolerance ppm -100 +100 symm symmetry (duty cycle) % 40 60 HDMP-1638 (trx) transceiver reference clock requirements t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v
8 symbol parameter units min. typ. max. v ih,pecl pecl input high voltage level v 2.14 2.42 v il,pecl pecl input low voltage level v 1.49 1.82 HDMP-1638 (trx) pecl dc electrical specifications t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v symbol parameter units min. typ. max. v ih,ttl ttl input high voltage level, guaranteed high signal v 2 5.5 for all inputs v il,ttl ttl input low voltage level, guaranteed low signal v 0 0.8 for all inputs v oh,ttl ttl output high voltage level, i oh = -400 m a v 2.2 v cc v ol,ttl ttl output low voltage level, i ol = 1 ma v 0 0.6 i ih,ttl input high current (magnitude), v in = 2.4 v, v cc = 3.45 v m a40 i il,ttl input low current (magnitude), v in = 0.4 v, v cc = 3.45 v m a -600 i cc,trx [1,2] transceiver v cc supply current, t a = 25 c ma 270 notes: 1. masurement conditions: tested sending 1250 mbd prbs 2^7-1 sequence from a serial bert with both d out outputs biased with 150 w resistors. 2. typical specified with v cc = 3.3 volts, maximum specified with v cc = 3.45 volts. HDMP-1638 (trx) dc electrical specifications t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v
9 figure 7: transmitter dout eye diagrams. symbol parameter units min. typ. max. t r,ttlin input ttl rise time, 0.8 to 2.0 volts nsec 2 t f,ttlin input ttl fall time, 2.0 to 0.8 volts nsec 2 t r,ttlout output ttl rise time, 0.8 to 2.0 volts, 10 pf load nsec 1.5 2.4 t f,ttlout output ttl fall time, 2.0 to 0.8 volts, 10 pf load nsec 1.1 2.4 t rs,hs_out hs_out single-ended (+dout) rise time psec 85 225 327 t fs,hs_out hs_out single-ended (+dout) fall time psec 85 200 327 t rd,hs_out hs_out differential rise time psec 85 327 t fd,hs_out hs_out differential fall time psec 85 327 v ip,hs_in hs_in input peak-to-peak differential voltage mv 200 1200 2000 v op,hs_out [1] hs_out output pk-pk diff. voltage (z0=50 w , fig. 10) mv 1200 1600 2200 note: 1.output peak-to-peak differential voltage specified as dout+ minus dout-. HDMP-1638 (trx) ac electrical specifications t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v 22.0680 ns yaxis = 400 mv/div a. differential hs_out output (dout+ minus dout? 22.0680 ns yaxis = 200 mv/div b. single-ended hs_out output (dout+) eye diagrams of the high-speed serial outputs from the HDMP-1638 as captured on the 83480a digital communications analyzer. tested with prbs=2 7 -1.
10 symbol parameter units typ. rj [1] random jitter at dout, the high speed electrical data port, specified as ps 8 1 sigma deviation of the 50% crossing point (rms) dj [1] deterministic jitter at dout, the high speed electrical data port (pk-pk) ps tbd HDMP-1638 (transmitter section) output jitter characteristics (measured with equivalent parts which have ttl refclk input) t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v note: 1. defined by fibre channel specification x3.230-1994 fc-ph standard, annex a, section a.4 and tested using measurement method shown in figure 8. figure 8: transmitter jitter measurement method. 70841b pattern generator* 83480a oscilloscope HDMP-1638 70311a clock source + data - data 0000011111 trigger ch1 ch2 +dout -dout refclk loopen tx[0..9] bias tee 1.4 v 0011111000 (static k28.7) 1.25 ghz 125 mhz * pattern generator provides a divide by 10 function. a. block diagram of rj measurement method 70841b pattern generator 83480a oscilloscope HDMP-1638 70311a clock source + data - data +k28.5, -k28.5 trigger ch1 ch2 +dout -dout refclk loopen tx[0..9] 1.25 ghz 125 mhz enbytsync rx[0..9] -din +din divide by 2 circuit divide by 10 circuit (dual output) variable delay ttl b. block diagram of dj measurement method
11 symbol parameter units typ. max. c input input capacitance on ttl input pins pf 1.6 symbol parameter units typ. max. p d, trx [1,2] transceiver power dissipation, one output pair open, mw 840 tbd parallel data has 5 ones and 5 zeroes. p d, trx [1,2,3] transceiver power dissipation, outputs connected per mw 890 tbd recommended bias terminations with idle pattern q jc [4] thermal resistance, junction to case c/w 10 HDMP-1638 (trx) thermal and power temperature characteristics t a = 0 c to +70 c, v cc = 3.15 v to 3.45 v notes: 1. p d is obtained by multiplying v cc by i cc and subtracting the power dissipated outside the chip at the high speed bias resistors. 2. typical specified with v cc = 3.3 volts, maximum value specified with v cc = 3.45 volts. 3. specified with high speed outputs biased with 150 w resistors and receiver ttl outputs driving 10 pf loads. 4. based on independent package testing by agilent technologies. q ja for these devices is 48 c/w for the HDMP-1638. q ja is measured on a standard 3x3 fr4 pcb in a still air environment. to determine the actual junction temperature in a given application, use the following: t j = t c +( q jc x pd), where t c is the case temperature measured on the top center of the package and p d is the power being dissipated. i/o type definition i-ttl input ttl, floats high when left open o-ttl output ttl hs_out high speed output, ecl compatible hs_in high speed input c external circuit node s power supply or ground pecl positive ecl i/o type definitions HDMP-1638 (trx) pin input capacitance
12 figure 9: o-ttl and i-ttl simplified circuit schematic. figure 10: hs_out and hs_in simplified circuit schematic. v cc _ttl r v bb 1.4 v r gnd_ttl v cc _ttl or v cc _rx esd protection gnd_ttl v cc _ttl r r o_ttl i_ttl gnd esd protection r v cc hs out r 0.01 ? 0.01 ? zo zo v cc _txhs v cc _txecl gnd esd protection -dout +dout 150 150 r pad r pad gnd_txhs +din -din esd protection r + + hs in 2 * z0 v cc gnd gnd v cc notes: 1. hs_in inputs should never be connected to ground as permanent damage to the device may result. 2. the optional series padding resistors (r pad ) help dampen load reflections. typical r pad values for mismatched loads range between 25-z0 w . 3. for pecl refclk input pair, the constant voltage supplies (shown as a) and resistors r are omitted. a
13 figure 11: HDMP-1638 (trx) package layout and marking, top view. rxcap0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 v cc _txhs HDMP-1638 fig 11 HDMP-1638 xxxx-x rz.zz s yyww 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 bytsync gnd_rxttl rx[0] rx[1] rx[2] v cc _rxttl rx[3] rx[4] rx[5] rx[6] v cc _rxttl rx[7] rx[8] rx[9] gnd_rxttl gnd_txhs tx[0] tx[1] tx[2] tx[3] tx[4] tx[5] tx[6] tx[7] tx[8] tx[9] nc rxsel gnd_txttl gnd_txa txcap1 doutb+ doutb- v cc _txecl douta+ douta- v cc _rx gnd_rxhs dinb+ dinb- v cc _rxhs dina+ dina- gnd_rxa v cc _rxa rxcap1 txcap0 v cc _txa loopen v cc _tx gnd +refclk -refclk enbytsync gnd nc v cc _rx v cc _rxttl rbc1 rbc0 gnd_rxttl xxxx-x = wafer lot number?uild number rz.zz = die revision s = supplier code yyww = date code (yy = year, ww = work week) country = country of manufacture (marked on back of device) *note: pins 12 and 27 are designated as "no connect" pins and are normally unconnected. sig_det
14 trx i/o definition name pin type signal byte sync output: an active high output. used to indicate detection of either a comma character (0011111xxx). it is only active when enbytsync is enabled. serial data inputs: high speed inputs. serial data is accepted from the dina inputs when loopen and rxsel are both low. serial data inputs: high speed inputs. serial data is accepted from the dinb inputs when loopen is low and rxsel high. serial input select: if this pin is held low then dina inputs are parallelized. if this pin is held high then dinb inputs are parallelized. serial data outputs: high speed outputs. these lines are active when loopen is set low. when loopen is set high, these outputs are held static at logic 1. if unused, remove the 150 w pulldown resistors to save power. serial data outputs: high speed outputs. these lines are active when loopen is set low. when loopen is set high, these outputs are held static at logic 1. if unused, remove the 150 ohm pulldown resistors to save power. enable byte sync input: when high, turns on the internal byte sync function to allow clock synchronization to a comma character (0011111xxx). when the line is low, the function is disabled and will not reset registers and clocks, or strobe the bytsync line. logic ground: normally 0 volts. this ground is used for internal pecl logic. it should be isolated from the noisy ttl ground as well as possible. analog ground: normally 0 volts. used to provide a clean ground plane for the receiver pll and high-speed analog cells. ground: normally 0 volts. ttl receiver ground: normally 0 volts. used for the ttl output cells of the receiver section. analog ground: normally 0 volts. used to provide a clean ground plane for the pll and high-speed analog cells. bytsync 47 o-ttl -dina 52 hs_in +dina 53 -dinb 55 hs_in +dinb 56 rxsel 13 i-ttl -douta 59 hs_out +douta 60 -doutb 62 hs_out +doutb 63 enbytsync 24 i-ttl gnd 21 s 25 gnd_rxa 51 s gnd_rxhs 57 s gnd_rxttl 32 s 33 46 gnd_txa 15 s
15 name pin type signal ground: normally 0 volts. ttl transmitter ground: normally 0 volts. used for the ttl input cells of the transmitter section. these pins are connected to an isolated pad and have no functionality. they may be left open, however, ttl levels may also be applied to these pins. loopback enable input: when set high, the high speed serial signal is internally wrapped from the transmitters serial loopback outputs back to the receivers loopback inputs. also when in loopback mode, the dout outputs are held static at logic 1. when set low, dout outputs and din inputs are active. receiver byte clocks: the receiver section recovers two 62.5 mhz receive byte clocks. these two clocks are 180 degrees out of phase. the receiver parallel data out- puts are alternately clocked on the rising edge of these clocks. the rising edge of rbc1 aligns with the output of the comma character (for byte alignment) when detected. reference clock and transmit byte clock: a 125 mhz clock supplied by the host system. the transmitter section accepts this signal as the frequency reference clock. it is multiplied by 10 to generate the serial bit clock and other internal clocks. the transmit side also uses this clock as the transmit byte clock for the incoming parallel data tx[0]..tx[9]. it also serves as the reference clock for the receive portion of the transceiver. data outputs: one 10 bit data byte. rx[0] is the first bit received. rx[0] is the least significant bit. when there is a loss of input signal at dinb and rxsel is high, these outputs are held static at logic 1. refer to sig_det (pin 26) pin definition for more details. loop filter capacitor: a loop filter capacitor for the internal pll must be connected across the rxcap0 and rxcap1 pins. (typical value = 0.1 m f) gnd_txhs 1 s gnd_txttl 14 s n/c 27,12 loopen 19 i-ttl rbc1 30 o-ttl rbc0 31 +refclk 22 pecl -refclk 23 rx[0] 45 o-ttl rx[1] 44 rx[2] 43 rx[3] 41 rx[4] 40 rx[5] 39 rx[6] 38 rx[7] 36 rx[8] 35 rx[9] 34 rxcap0 48 c rxcap1 49
16 data inputs: one 10 bit, 8b/10b encoded data byte. tx[0] is the first bit transmitted. tx[0] is the least significant bit. loop filter capacitor: a loop filter capacitor must be connected across the txcap1 and txcap0 pins (typical value=0.1 m f). signal detect: indicates a loss of signal on the high-speed differential inputs, dinb, as in the case where the transmission cable becomes disconnected. if din>=200 mv peak-to-peak, sig_det=logic 1. if din<200 mv and din>50 mv, sig_det=undefined. if din<=50 mv, sig_det=logic 0. logic power supply: normally 3.3 volts. used for internal receiver pecl logic. it should be isolated from the noisy ttl supply as well as possible. analog power supply: normally 3.3 volts. used to provide a clean supply line for the pll and high speed analog cells. high speed supply: normally 3.3 volts. used only for the high speed receiver cell (hs_in). noise on this line should be minimized for best operation. ttl power supply: normally 3.3 volts. used for all ttl receiver output buffer cells. logic power supply: normally 3.3 volts. used for internal transmitter pecl logic. also used for all transmitter ttl input buffer cells. analog power supply: normally 3.3 volts. used to provide a clean supply line for the pll and high speed analog cells. high speed ecl supply: normally 3.3 volts. used only for the last stage of the high speed transmitter output cell (hs_out) as shown in figure 10. due to high current transi- tions, this v cc should be well bypassed to a ground plane. high speed supply: normally 3.3 volts. used by the transmitter side for the high speed circuitry. noise on this line should be minimized for best operation. name pin type signal tx[0] 2 i-ttl tx[1] 3 tx[2] 4 tx[3] 5 tx[4] 6 tx[5] 7 tx[6] 8 tx[7] 9 tx[8] 10 tx[9] 11 txcap0 17 c txcap1 16 v cc _tx 20 s sig_det 26 o-ttl v cc _rx 28 s 58 v cc _rxa 50 s v cc _rxhs 54 s v cc _rxttl 29 s 37 42 v cc _txa 18 s v cc _txecl 61 s v cc _txhs 64 s
17 figure 12: power supply bypass. start up procedure: the transceiver startup procedure(s) and the following conditions: v cc = +3.3 v 5 % and refclk = 125 mhz 100 ppm. after the above conditions have been met, apply valid data using a balanced code such as 8b/10b. frequency lock occurs within 500 m s. after frequency lock, phase lock occurs within 2500 bit times. transceiver power supply bypass and loop filter capacitors if desired, bypass capacitors may be used on the power supply pins of the HDMP-1638. all bypass chip capacitors are 0.1 m f. the v cc _rxa and v cc _txa pins are the analog power supply pins for the pll sections. the supply into these pins should be clean with minimum noise. use of capacitors as shown in figure 12 is mandatory for these pins. the pll loop filter capacitors and their pin locations are also shown on figure 12. notice that only two capacitors are required; c pllt for the transmitter and c pllr for the receiver. nominal capacitance is 0.1 m f. the maximum voltage across the capacitors is on the order of 1 volt, so the capacitor can be a low voltage type and physically small. the pll capacitors are to be placed physically close to the appropriate pins on the HDMP-1638. keeping the lines short will prevent them from picking up any stray noise from surrounding lines or components. rxcap0 v cc _rxttl v cc _rxttl v cc _txhs top view gnd_rxttl gnd_txhs gnd_txa txcap1 v cc _txecl v cc _rx gnd_rxhs gnd_rxa v cc _rxa rxcap1 * supply voltage into v cc _rxa and v cc _txa should be from a low noise source. all bypass capacitors and pll filter capacitors are 0.1 ?. v cc _tx gnd v cc v cc gnd_rxttl txcap0 v cc _txa gnd gnd_rxttl v cc _rxttl v cc _rx c pllt v cc * c pllr v cc HDMP-1638 gnd_txttl v cc * v cc _rxhs
figure 13: mechanical dimensions of HDMP-1638. package information item details package material plastic lead finish material 85% tin, 15% lead lead finish thickness 300C800 m m lead coplanarity 0.08 mm max mechanical dimensions a1 a2 pin #1 a1 a2 b1 b4 b3 c1 b2 all dimensions are in millimeters. b5 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 HDMP-1638 top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c3 part number a1 a2 b1 b2 b3 b4 b5 c1 c2 c3 HDMP-1638 10.00 13.20 0.22 0.50 0.88 0.17 0.25 2.00 0.25 min. 2.45 tolerance ?0.10 ?0.25 ?0.05 basic + 0.15/ ?0.10 max. + 0.10/ ?0.05 max. c2 18
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies, inc. 5968-5120e (11/99)

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